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datasheet 9dbv0731 revision d 03/28/16 1 ?2016 integrated device technology, inc. 7-output 1.8v hcsl fanout buffer 9dbv0731 description the 9dbv0731 is a member of idt's full-featured pcie family. the device has 7 output enables for clock management, and 3 selectable smbus addresses. recommended application pcie gen1-3 clock distributi on in storage, networking, compute, consumer output features ? 7 - 1-200mhz low-power (lp) hcsl dif pairs ? easy ac-coupling to other logic families, see idt application note an-891 key specifications ? additive cycle-to-cycle jitter <5ps ? output-to-output skew < 60ps ? additive phase jitter is <100fs rms for pcie gen3 ? additive phase jitter <300fs rms (12khz-20mhz @125mhz) features/benefits ? lp-hcsl outputs; saves 14resistors and 24mm 2 compared to standard hcsl ? 41mw typical power consumpt ion; elminates thermal concerns ? outputs can optionally be supplied from any voltage between 1.05v and 1.8v; maximum power savings ? oe# pin for each output; support dif power management ? hcsl-compatible differential input; can be driven by common clock sources ? smbus-selectable features a llow optimization to customer requirements ? slew rate for each output; allows tuning for various line lengths ? differential output amplitude; allows tuning for various application environments ? 1mhz to 200mhz operating frequency ? 3.3v tolerant smbus interface works with legacy controllers ? selectable smbus addresses; mu ltiple devices can easily share an smbus segment ? device contains default confi guration; smbus interface not required for device operation ? space saving 40-pin 5x5mm vfqfpn; minimal board space block diagram control logic ^ckpwrgd_pd# sdata_3.3 voe(6:0)# sclk_3.3 vsadr clk_in 7 dif6 ` dif4 dif3 dif1 dif0 clk_in# dif2 dif5
7-output 1.8v hcsl fanout buffer 2 revision d 03/28/16 9dbv0731 datasheet pin configuration smbus address selection table power management table power connections ^ckpwrgd_pd# vddio voe5# dif5# dif5 voe4# dif4# dif4 vddio vdd1.8 40 39 38 37 36 35 34 33 32 31 vsadr_tri 130 nc voe6# 229 voe3# dif6 328 dif3# dif6# 427 dif3 vddr1.8 526 vddio clk_in 625 vdd1.8 clk_in# 724 voe2# gnddig 823 dif2# sclk_3.3 922 dif2 sdata_3.3 10 21 voe1# 11 12 13 14 15 16 17 18 19 20 vdddig1.8 vddio voe0# dif0 dif0# vdd1.8 vddio dif1 dif1# nc 40-vfqfpn ^ pref ix indicates internal pull-up resistor v pref ix indicates internal pull-dow n resistor 5mm x 5mm 0.4mm pin pitch 9dbv0731 connect epad to gnd sadr address 0 1101011 m 1101100 1 1101101 x x x state of sadr on first application of ckpwrgd_pd# + read/write bit true o/p comp. o/p 0xxxlowlow 1 running 0 x low low 1 running 1 0 running running 1 running 1 1 low low clk_in difx oex# pin ckpwrgd_pd# smbus oex bit vdd vddio gnd 541 input receiver analo g 11 8 digital power 16, 25, 31 12,17,26,32,39 41 dif outputs, logic description pin number
revision d 03/28/16 3 7-output 1.8v hcsl fanout buffer 9dbv0731 datasheet pin descriptions pin # pin name pin type description 1 vsadr_tri latched in tri-level latch to select smbus address. see smbus address selection table. 2voe6# in active low input for enabling dif pair 6. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 3 dif6 out differential true clock output 4 dif6# out differential complementary clock output 5 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 6 clk_in in true input for differential reference clock. 7 clk_in# in complementary input for differential reference clock. 8 gnddig gnd ground pin for digital circuitry 9 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 10 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 11 vdddig1.8 pwr 1.8v digital power (dirty power) 12 vddio pwr power supply for differential outputs 13 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 14 dif0 out differential true clock output 15 dif0# out differential complementary clock output 16 vdd1.8 pwr power supply, nominal 1.8v 17 vddio pwr power supply for differential outputs 18 dif1 out differential true clock output 19 dif1# out differential complementary clock output 20 nc n/a no connection. 21 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 22 dif2 out differential true clock output 23 dif2# out differential complementary clock output 24 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 vdd1.8 pwr power supply, nominal 1.8v 26 vddio pwr power supply for differential outputs 27 dif3 out differential true clock output 28 dif3# out differential complementary clock output 29 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 30 nc n/a no connection. 31 vdd1.8 pwr power supply, nominal 1.8v 32 vddio pwr power supply for differential outputs 33 dif4 out differential true clock output 34 dif4# out differential complementary clock output 35 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 36 dif5 out differential true clock output 37 dif5# out differential complementary clock output 38 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 39 vddio pwr power supply for differential outputs 40 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 41 epad gnd connect paddle to ground.
7-output 1.8v hcsl fanout buffer 4 revision d 03/28/16 9dbv0731 datasheet test loads alternate terminations the 9dbv0731 can easily drive l vpecl, lvds, and cml logic. see ?an-891 driving lvpecl, lvds , and cml logic with idt's "universal" low-power hcsl outputs? for details. rs rs low-power differential output test load 2pf 2pf 5 inches zo=100w ? alternate differential output terminations rs zo units 33 100 27 85 ohms
revision d 03/28/16 5 7-output 1.8v hcsl fanout buffer 9dbv0731 datasheet absolute maximum ratings stresses above the ratings lis ted below can cause permanent damage to the 9d bv0731. these ratings, which are standard values for idt commercially rated parts, are stress ratings on ly. functional operation of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for extended periods ca n affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes supply voltage vddx applies to vdd, vdda and vddio -0.5 2.5 v 1,2 input voltage v in -0.5 v dd +0.5 v 1,3 input high voltage, smbus v ihsmb smbus clock and data pins 3.3 v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 2.5v. ta = t com or t ind ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes input crossover voltage - dif_in v cross cross over voltage 150 900 mv 1 input swing - dif_in v swing differential value 300 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua input duty cycle d tin measurement from differential wavefrom 40 60 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero
7-output 1.8v hcsl fanout buffer 6 revision d 03/28/16 9dbv0731 datasheet electrical characteristics?input/supply /common parameters?normal operating conditions ta = t com or t ind ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddx supply voltage for core and analog 1.7 1.8 1.9 v output supply voltage vddio low voltage supply lp-hcsl outputs 0.9975 1.05-1.8 1.9 v t com commmercial r ange 0 25 70 c 1 t ind industrial range -40 25 85 c 1 input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v input mid voltage v im single-ended tri-level inputs ('_tri' suffix) 0.4 v dd 0.6 v dd v input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua input frequency f in 1 200 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c i ndi f_i n dif_in differential clock inputs 1.5 2.7 pf 1,6 c ou t output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 input ss modulation frequency pcie f modi npci e allowable frequency for pcie applications (triangular modulation) 30 33 khz input ss modulation frequency non-pcie f modi n allowable frequency for non-pcie applications (triangular modulation) 066khz oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 2 trise t r rise time of single-ended control inputs 5 ns 2 smbus input low voltage v ilsmb v ddsmb = 3.3v, see note 4 for v ddsmb < 3.3v 0.8 v 4 smbus input high voltage v ihsmb v ddsmb = 3.3v, see note 5 for v ddsmb < 3.3v 2.1 3.3 v 5 smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb bus voltage 1.7 3.6 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 7 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 3 time from deassertion until outputs are >200 mv 4 for v ddsmb < 3.3v, v ilsmb <= 0.35v ddsmb 5 for v ddsmb < 3.3v, v ihsmb >= 0.65v ddsmb 6 dif_in input 7 the differential input clock must be running for the smbus to be active capacitance ambient operating temperature input current
revision d 03/28/16 7 7-output 1.8v hcsl fanout buffer 9dbv0731 datasheet electrical characteristics? dif low-power hcsl outputs electrical characteristi cs?current consumption ta = t com or t ind ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes scope avera g in g on 3.0v/ns settin g 2.3 3.4 4.3 v/ns 1,2,3 scope averaging on 2.0v/ns setting 1.4 2.2 3.1 v/ns 1,2,3 slew rate matching trf slew rate matching, scope averaging on 5 20 % 1,2,4 voltage high v hi gh 660 774 850 7 voltage low v low -150 0 150 7 max voltage vmax 813 1150 7 min voltage vmin -300 -55 7 vswing vswing scope averaging off 300 1548 mv 1,2 crossing voltage (abs) vcross_abs scope averaging off 250 404 550 mv 1,5 crossing voltage (var) -vcross scope averaging off 12 140 mv 1,6 2 measured from differential waveform 4 matching applies to rising edge rate for clock and fa lling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# fa lling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. 7 660mv vhigh is the minimum when vddio is >= 1.05v +/-5%. if vddio is < 1.05v +/-5%, the minimum vhigh will be vddiomin - 250mv. for example for vddio = 0.9v +/-5%, vhighmin will be 860mv - 250mv = 610mv. statistical measurement on single-ended signal using oscilloscope math function. (scope mv measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. c l = 2pf with r s = 33 ? for zo = 50 ? (100 ? differential trace impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. slew rate trf ta = t com or t ind ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i ddaop vddr @ 100mhz 2.5 5 ma 1 i dddop vddig, all outputs @100mhz 4.6 7 ma 1 i ddi oop vdd1.8+vddio, all outputs @100mhz 27 32 ma 1 i ddpd vddr, ckpwrgd_pd# = 0 0.4 0.7 ma 1, 2 i ddd z vdddig, ckpwrgd_pd# = 0 0.4 0.8 ma 1, 2 i ddi odz vdd1.8+vddio, ckpwrgd_pd# = 0 0.0 0.1 ma 1, 2 1 guaranteed by design and characterization, not 100% tested in production. 2 input clock stopped. operating supply current powerdown current
7-output 1.8v hcsl fanout buffer 8 revision d 03/28/16 9dbv0731 datasheet electrical characteristics?ou tput duty cycle, jitter, sk ew and pll characteristics electrical characteristics? phase jitter parameters ta = t com or t ind ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes duty cycle distortion t dcd measured differentially, @100mhz -1 -0.1 0.5 % 1,3 skew, input to output t p dbyp v t = 50% 1800 2342 3000 ps 1 skew, output to output t sk3 v t = 50% 37 60 ps 1,4 jitter, cycle to cycle t jcyc-cyc additive jitter 0.1 5 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform 3 duty cycle distortion is the difference in duty cycle betw een the output and the input clock when the device is operated in bypass mode. 4 all outputs at default slew rate ta = t com or t ind ; supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jp hpcieg1 pcie gen 1 0.1 5 n/a ps (p-p) 1,2,3,5 pcie gen 2 lo band 10khz < f < 1.5mhz 0.1 0.4 n/a ps (rms) 1,2,3,4,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.01 0.4 n/a ps (rms) 1,2,3,4 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.00 0.1 n/a ps (rms) 1,2,3,4 t jphsgmiim0 125mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 165 200 n/a fs (rms) 1,6 t jphsgmiim1 125mhz, 12khz to 20mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 251 300 n/a fs (rms) 1,6 1 guaranteed by design and characterization, not 100% tested in production. 4 for rms figures, additive jitter is calculated by solving the following equation: additive jitter = sqrt[(total jitter)^2 - (i nput jitter)^2] 5 driven by 9fgv0831 or equivalent 6 rohde&schwarz sma100 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. additive phase jitter t jphpcieg2
revision d 03/28/16 9 7-output 1.8v hcsl fanout buffer 9dbv0731 datasheet additive phase jitter plo t: 125m (12khz to 20mhz)
7-output 1.8v hcsl fanout buffer 10 revision d 03/28/16 9dbv0731 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: read/write address is latched on sadr pin. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
revision d 03/28/16 11 7-output 1.8v hcsl fanout buffer 9dbv0731 datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 dif oe5 output enable rw low/low oe# pin control 1 bit 6 dif oe4 output enable rw low/low oe# pin control 1 bit 5 1 bit 4 dif oe3 output enable rw low/low oe# pin control 1 bit 3 dif oe2 output enable rw low/low oe# pin control 1 bit 2 dif oe1 output enable rw low/low oe# pin control 1 bit 1 1 bit 0 dif oe0 output enable rw low/low oe# pin control 1 1. a low on these bits will overide the oe# pin and force the differential output low/low smbus table: pll operating mode and output amplitude control register byte 1 name control function type 0 1 default bit 7 0 bit 6 1 bit 5 dif oe6 output enable rw low/low oe# pin control 1 bit 4 0 bit 3 1 bit 2 1 bit 1 amplitude 1 rw 00 = 0.6v 01 = 0.7v 1 bit 0 amplitude 0 rw 10= 0.8v 11 = 0.9v 0 1. a low on the dif oe bit will overide the oe# pin and force the differential output low/low smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 slewratesel dif5 adjust slew rate of dif5 rw slow setting fast setting 1 bit 6 slewratesel dif4 adjust slew rate of dif4 rw slow setting fast setting 1 bit 5 1 bit 4 slewratesel dif3 adjust slew rate of dif3 rw slow setting fast setting 1 bit 3 slewratesel dif2 adjust slew rate of dif2 rw slow setting fast setting 1 bit 2 slewratesel dif1 adjust slew rate of dif1 rw slow setting fast setting 1 bit 1 1 bit 0 slewratesel dif0 adjust slew rate of dif0 rw slow setting fast setting 1 smbus table: dif slew rate control register byte 3 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 0 bit 4 0 bit 3 0 bit 2 1 bit 1 1 bit 0 slewratesel dif6 adjust slew rate of dif6 rw slow setting fast setting 1 byte 4 is reserved and reads back 'hff reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved controls output amplitude reserved reserved reserved
7-output 1.8v hcsl fanout buffer 12 revision d 03/28/16 9dbv0731 datasheet smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 1 bit 6 device type0 r 1 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 0 bit 2 device id2 r 1 bit 1 device id1 r 1 bit 0 device id0 r 1 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 reserved 000111 binary or 07 hex 00 = fgv, 01 = dbv, 10 = dmv, 11= dbv fanout only device id a rev = 0000 revision id byte count programming 0001 = idt writing to this register will configure how many bytes will be read back, default is = 8 bytes. reserved reserved device type vendor id
revision d 03/28/16 13 7-output 1.8v hcsl fanout buffer 9dbv0731 datasheet marking diagrams notes: 1. ?lot? is the lot sequence number. 2. ?coo? denotes country of origin. 3. yyww is the last two digits of the year and week that the part was assembled. 4. line 2: truncated part number 5. ?l? denotes rohs compliant package. 6. ?i? denotes industrial temperature range device. thermal characteristics ics dbv0731al yyww coo lot ics bv0731ail yyww coo lot parameter symbol conditions pkg typ value units notes jc junction to case 42 c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 27 c/w 1 1 epad soldered to board thermal resistance ndg40
7-output 1.8v hcsl fanout buffer 14 revision d 03/28/16 9dbv0731 datasheet package outline and dimensions (ndg40). use epad option p1.
revision d 03/28/16 15 7-output 1.8v hcsl fanout buffer 9dbv0731 datasheet package outline and dimensions (ndg40), cont. use epad option p1.
7-output 1.8v hcsl fanout buffer 16 revision d 03/28/16 9dbv0731 datasheet ordering information "lf" suffix to the part number are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (wil l not correlate with the datasheet revision). revision history part / order number shipping packaging package temperature 9DBV0731AKLF trays 40-pin vfqfpn 0 to +70 c 9DBV0731AKLF tape and reel 40-pin vfqfpn 0 to +70 c 9dbv0731akilf trays 40-pin vfqfpn -40 to +85 c 9dbv0731akilf tape and reel 40-pin vfqfpn -40 to +85 c rev. initiator issue date description page # a rdw 7/28/2014 1. updated front page text 2. updated block diagram 3. updated electrical tables 4. updated test loads diagrams. 5. updated smbus byte 2, 3 and 6 labeling. functionality did not change. 6. move to final. various b rdw 8/27/2014 1. updated min vhigh on dif outputs from 630mv to 660mv, correcting a typo. 7 c rdw 8/28/2014 1. corrected supply voltage in absolute maximim ratings. 2. lowered additive phase jitter specs. various d rdw 3/28/2016 1. revised front page text extensively. 2. added note about spread spectrum compatibility to the features. 3. change pin names of vdda1.8 to vdd1.8 to clarify that this part does not have a pll. this is a document change only. there is no silicon change. 4. corrected oe6# to indicate an internal pull down, not a pull up. 5. added epad nomenclature to ds 6. updated package drawing to lastest version - no package change. 7. added reference to an-891. 8. updated "current consumption" table to remove references to vdda1.8 9. added "rms additive phase jitter: 251fs" to phase noise plot 10. updated "clock input parameters" table for consistency - no silicon change. 11. updated "output duty cycle, jitter, skew and pll characteristics" and "phase jitter" tables to remove references to bypass mode. 1-5,7-9 14
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support www.idt.com/go/support

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